1. Field of the Invention
This invention generally relates to a high-voltage level-translation circuit structure and method, and more particularly, to a high-voltage level-translation circuit structure and method suitable for use in high-voltage MOS integrated circuit type applications.
2. Brief Description of the Prior Art
Complementary N and P channel MOS devices have been commonly used for active pull-up and pull-down operation in power driven circuitry. For supply voltages greater than about 50 volts, the P and N channel gates of the complementary driver devices are usually driven separately in order to avoid excessive gate voltages. This separate operation or excitation requires high-voltage level-shifting or level-translation circuitry to translate a ground-reference logic signal to a high-voltage reference logic signal to drive one of these push-pull devices. Discrete type level translation devices usually involve the additional use of an optoelectronic isolation, a resistor and zener voltage divider, or capacitive coupling circuitry. These approaches are either incompatible with silicon integrated circuitry, inefficient in using silicon real estate, or involve substantial performance trade-offs.
Thus, a need has existed to provide improved high-voltage level translation circuitry for drawing serially-connected high-voltage MOS transistors. In particular, a need has existed to provide high-voltage level-translation circuitry suitable for monolithic integration without substantial loss of performance.